Program controlled data processing system

ABSTRACT

A program controlled data processor system which employs functionally equivalent first and second control units on a mutually exclusive basis to control an input-output system. The processor system comprises a plurality of independent memory units and communication between the control means and the independent memory units is by way of communication paths which may be selectively associated with any of the memory units and with either of the control means. The processor arrangement includes means for insuring that the two control means simultaneously carry out identical work functions.

United States Patent Downing et al.

[ Mar. 21, 1972 [54] PROGRAM CONTROLLED DATA PROCESSING SYSTEM [72]Inventors: Randall W. Downing; John S. Nowak, both of Wheaton; Frank F.Taylor, West Chicago; Werner Ulrich, Glen Ellyn, all of Ill.

[73] Assignee: Bell Telephone Laboratories, Incorporated,

New York, NY.

[22] Filed: Nov. 24, 1967 [2]] Appl. No.: 685,636

Related US. Application Data [62] Division ot'Ser. No. 334,875, Dec. 31,I963.

[52] [1.8. CI. ..340/l72.5 [5 1] Int. Cl. A ...G06i /16 [58] FieldofSearch ..340/l72.5; 235/157 [56] References Cited UNITED STATESPATENTS 3,303,474 2/1967 Moore et al. ...34O/l 72 5 3,253,262 5/1966Wilenitz et al ..340ll72.5 3,25 l ,040 5/l966 Burkholder et al. ..340/l72,5 3,263,2l9 7/l 966 Brun et al. ..340/l 72.5

Primary ExaminerGareth D. Shaw Attorney-R1. Guenther and R. B. Ardis[57] ABSTRACT 55 Claims, 89 Drawing Figures UNI VE 9514A l I r/ewvxFRAME 1 l m. I mun 1r 501w m ,5, UM ggggg 1m 510041 0/502 0/574 126 001-l NETWORK FRAME l l zgyfi gf E 136 0451.5 Rat 1a L la? 1 au/vcroe l 1 1m8 saw/c5 123 FRAME 27 l '92. CC 73 {63 U/VE saw i uwvcr saw .1 1 l LWSCELLANEW l NETW 00/1/17? I26 SIGNAL 0150? l NET/1r. cowm- TWA/K FRAMECABLE RCl R T CABLE RCl R I CABLERCl R l 133 mu/vx sen/v L V 7 13 My l129 1132 5101x 41 0 5051 011045 RCV/i. 111 40 137 J my] 104 1/0 104 104104 111145091? SCANNER PAIENTED m 2 1 m2 SHEET 01UF86 PATENTEDHARZI I9723.651 .480

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1. A program controlled data handling system comprising: a processorarrangement comprising a control arrangement, a plurality of independentmemories containing sequences of program order words and data and atransmission arrangement for selectively interconnecting said memoriesand said control arrangement; and an input-output system connected tothe processor arrangement and responsive to command signals therefrom;said control arrangement comprises two functionally equivalent controlmeans, said transmission arrangement comprises a plurality ofindependent transmission buses for selectively connecting said controlmeans and said memories to form two processor combinations, eachprocessor combination comprising a selected one of said control means,selected ones of said memories and selected ones of said transmissionbuses; and said system further comprises circuits for assuring theconcurrent performance of identical work functions by said two controlmeans and circuits for inhibiting the transmission of command signalsfrom one of said control means to said inputoutput system.
 2. A programcontrolled data handling system in accordance with claim 1, wherein eachof said transmission buses comprises a plurality of paralleltransmission paths transformer-coupled to said memories and to saidcontrol arrangement.
 3. A program controlled data processing systemcomprising: a central processor having first and second independentcentral controls each having an active and a standby state; a clockoscillator in each of said central controls for generating oscillatoroutput signals; bistable means in each of said central controls fordefining the active and standby states of said central controls; meansfor controlling each of said bistable means, said controlling meansconcurrently sets the bistable means in the first central control to afirst state and resets the bistable means in the second central controlto a second state or concurrently resets the bistable means in the firstcentral control to the second state and sets the bistable means in thesecond central control to the first state; clock means in each of saidcentral controls responsive to clock oscillator output signals forgenerating clock signals defining central control machine cycles; andgating means responsive to the states of said bistable means forselectively connecting either of said oscillators to both of said clockmeans.
 4. A system in accordance with claim 3 wherein each of said clockmeans generates clock phasing signals, and said gating means furthercomprises means for gating said clock phasing signal of the centralcontrol which has its bistable means in the first stable state to aphasing input terminal of the clock means in the central control whichhas its bistable means in the second state.
 5. A system in accordancewith claim 3 wherein said gating means is responsive to a first statesignal from said bistable means of said first central control and to asecond state signal of said bistable means of said second centralcontrol to connect said oscillator in said first central control to saidclock means in both said first and said second central controls, andwherein said gating means is responsive to a first state signal fromsaid bistable means of said second central control and a second statesignal of said bistable means of said first central control to connectsaid oscillator means of said second central control to said clock meansin both said first central control and said second central control.
 6. Acentral processor of a program controlled data handling systemcomprising: first and second central controLs, means for placing saidfirst and second central controls in an active unit state on a mutuallyexclusive basis; each of said central controls comprising an oscillator,and clock means responsive to oscillator output signals for generatingclock timing signals and for generating clock phasing signals; andgating means for selectively gating output signals of the oscillator ofthe currently active central control to input terminals of said clockmeans in both of said central controls, and for connecting the clockphasing output signals of the clock circuit of the active centralcontrol to a phasing input terminal of the clock means of the standbycentral control. and gating means for connecting output signals of theoscillator of the currently active central control to input terminals ofsaid clock means in both of said central controls, and for connectingthe clock phasing output signals of the clock circuit of the activecentral control to a phasing input of the clock means of the standbycentral control.
 7. In a data processing system, a central processorsystem comprising an active central processor and a standby centralprocessor, means in said central processor system for causing saidactive central processor and said standby central processor toconcurrently carry out identical system functions, means in each of saidcentral processors for detecting faulty operation therein and forgenerating trouble signals upon detection of trouble, and means fortransmitting said trouble signals from each of said central processorsto the other of said central processors, and means in each of saidcentral processors responsive to said trouble signals for carrying outidentical central processor remedial actions.
 8. In combination, acentral processor system, said central processor system comprising anactive central processor and a standby central processor, means in saidcentral processor system for causing said active central processor andsaid standby central processor to concurrently perform the same systemwork functions, means for selectively comparing data words concurrentlygenerated in said active central processor and said standby centralprocessor and for generating a trouble signal when said data words donot agree.
 9. The combination in accordance with claim 8 wherein saidmeans for comparing comprises an internal transmission bus within eachof said central processors and gating means within each of said centralprocessors for gating information from a plurality of locations withinsaid central processor to said internal bus, a matching circuit in eachof said central processors, transmission means for transmitting theinformation on each of said internal buses to the matching circuit ofthe other central control, and means within each of said centralcontrols for gating information from said selected one of said pluralityof locations within said central control to said match circuit withinsaid central control, said match circuit comprising means for recordingsaid information transmitted from said other central control, means forrecording said information gated from said selected one of saidplurality of locations within said central control, and means forcomparing the contents of said recording means, said comparing meansresponsive to said contents for generating a trouble signal.
 10. Incombination, a central control system comprising first and secondcentral controls, means in said central control system defining anactive central control and a standby central control, a program storecontaining sequences of program order words, certain of said programsequences being normal data processing program sequences and others ofsaid sequences being maintenance program order word sequences, each ofsaid central controls comprising means for obtaining said sequences oforder words from said program store and means for executinG saidsequences, each of said central controls comprising registers forstoring said program order words and a plurality of flip-flop registers,said active central control including means responsive to certain ofsaid sequences of maintenance program order words for generating centralcontrol write command signals, said command signals comprising an orderportion and a data portion, means for transmitting said central controlwrite command signals to said standby central control, decoding means insaid standby central control responsive to said order portion of saidcentral control write command signals for storing in selected ones ofsaid registers said data portion of said command signal.
 11. Incombination, a central processor system comprising an active centralprocessor and a standby central processor, means in said centralprocessor system for causing said active central processor and saidstandby central processor to concurrently perform the same system workfunctions, a plurality of operational checking means within each of saidcentral processors for detecting a plurality of classes of faultyresponses of said central processors and for generating trouble signalsdiscrete to the class of faulty response detected, means fortransmitting said trouble signals from a central processor detecting afaulty response to the other central processor, means in each of saidcentral processors for recording said trouble signals and means forselectively inhibiting the transmission of said trouble signals.
 12. Thecombination in accordance with claim 11 wherein said means forinhibiting the transmission of trouble signals comprises a flip-flop ineach of said central processors.
 13. A central data processor systemcomprising an active central processor and a standby central processoreach comprising a plurality of match points, means in said centralprocessor system for causing said active central processor and saidstandby central processor to concurrently perform the same sequences ofsystem work functions, matching means for comparing match points in saidactive processor with corresponding match points in said standbyprocessor, means for generating a trouble signal when compared matchpoints do not agree, and match control circuitry defining the particularmatch points to be compared.
 14. A central data processor system inaccordance with claim 13 wherein said central processor system comprisesmeans responsive to said trouble signals for momentarily interruptingthe performance of said sequences of system work functions and othermeans for performing remedial work functions in each of said centralprocessors, and means responsive to said trouble signal for inhibitingsaid matching means.
 15. A central data processor system comprising anactive central processor and a standby central processor, means in saidcentral processor system for causing said active central processor andsaid standby central processor to concurrently perform the same systemwork functions, matching means comprising first and second matchregisters and a match circuit for comparing the contents of saidregisters and for generating a trouble signal when said comparedcontents do not agree, a plurality of corresponding data word sources ineach of said central processors, a match control circuit for selectivelygating information from corresponding data word sources of said activeand said standby processor to said first and said second match registersrespectively.
 16. A program controlled central processor system forperforming a plurality of classes of work functions comprising an activecentral processor and a standby central processor, means in said centralprocessor system for causing said active central processor and saidstandby central processor to concurrently perform the same workfunctions, register means for recording the class of work funCtioncurrently being performed in said central processors, a plurality ofcorresponding data word sources in each of said central processors,matching means for comparing data words and for generating a troublesignal when compared data words do not agree, a match control circuitfor selectively gating data words from corresponding data word sourcesof said active and said standby central processors to said matchingmeans in accordance with the contents of said class of work registermeans.
 17. A central processor system in accordance with claim 16further comprising a plurality of control and supervisory circuits andwherein each of said central processors comprises a program storecontaining sequences of program order words, a data store containingpluralities of data words, and a central control for obtaininginformation from said stores, for writing information into said datastore and for executing said programs obtained from said program storeand wherein said classes of work comprise: a. execution of program orderwords for generating signals for controlling said control andsupervisory circuits, b. execution of program order words for readinginformation from said data store, c. execution of transfer orders, d.execution of rereading of the program store or of the data store, and e.execution of work functions other than (a) thru (d) above.
 18. A centralprocessor system in accordance with claim 16 wherein said match controlcircuit comprises means responsive to certain states of said registermeans for cyclically obtaining from said active and said standby centralprocessor data words from selected data word sources in each of saidcentral processors.
 19. A system in accordance with claim 18 whereinsaid means for cyclically obtaining comprises a binary counter, and saidcentral processor system comprises clock means defining machine cyclesand means for incrementing said binary counter by a count of 1 duringeach machine cycle in which said register means is in said certainstates.
 20. A central processor system for performing a plurality ofwork functions comprising an active central processor and a standbycentral processor, means in said central processor system for causingsaid active central processor and said standby central processor toconcurrently perform the same work functions, a plurality ofcorresponding data word sources in each of said central processors,matching means comprising first and second match registers, a matchcircuit for comparing the contents of said registers for generating atrouble signal when said compared contents do not agree, a match controlcircuit, mode control register means for determining a plurality ofmodes of operation of said match control circuit, said modes including aroutine matching mode and a plurality of maintenance modes, said matchcontrol circuit responsive to the contents of said mode control registerfor selectively gating information from said plurality of data wordsources to said first and said second match registers.
 21. A centralprocessor system comprising an active central processor and a standbycentral processor, means in said central processor system for causingsaid active central processor and said standby central processor toconcurrently perform the same sequences of system work functions, aplurality of corresponding data word sources in each of said centralprocessors, matching means for comparing data words obtained fromcorresponding data word sources within each of said central processors,means for generating a trouble signal when said compared data words donot agree, operational checking means for detecting improper actions ofsaid central processor system and for generating a fault signal uponoccurrence of an improper action, means responsive to said fault signalfor causing each of said central processors to concurrently carry outthE same remedial work functions, and means responsive to a fault signaloccurring during a remedial work function to inhibit said matchingmeans.
 22. A data processing system comprising an active centralprocessor and a standby central processor, each of said centralprocessors comprising a program store containing sequences of programorder words, a data store and a central control, means in each of saidcentral controls for obtaining information from said program stores andfrom said data stores and for executing said sequences of program orderwords to perform system work functions, means in said data processingsystem for causing said active central processor and said standbycentral processor to concurrently perform the same system workfunctions, operational checking means for checking the validity ofinformation obtained from said program store and for generating firstand second signals representative of a valid program store response andan invalid program store response respectively, remedial meansresponsive to said second signal for causing both of said centralprocessors to generate reread commands to reread their respectiveprogram stores at the memory location from which the invalid responsewas obtained, said operational checking means being responsive to saidinformation obtained by said reread command to generate said first andsaid second signals, means responsive to the enablement of said remedialmeans and said first signal of said operational checking means forcomparing the information obtained by said active and said standbycentral processors from their respective program stores in response tosaid reread commands.
 23. A data processing system in accordance withclaim 22 wherein said central processor system comprises meansresponsive to said remedial means and to said second signal forrecording a data word representative of the location in said programstore from which the invalid response was obtained.
 24. In a dataprocessing system a central processor system comprising an activecentral processor and a standby central processor, means in said centralprocessor system for causing said active central processor and saidstandby central processor to concurrently perform the same sequences ofsystem work functions, matching means for comparing data wordsselectively obtained from a plurality of locations within each of saidcentral processors, means for generating a trouble signal when saidcompared data words do not agree, a match control circuit comprising apoint match register and a time match register, means in said centralprocessor system for setting said point match register and said timematch register to selected states, and means responsive to the states ofsaid point match register and said time match register for selectivelygating information to said matching means from the locations defined bythe states of said point match register at a time defined by the statesof said time match register.
 25. A central processor system comprisingan active central processor and a standby central processor, means insaid central processor system for causing said active central processorand said standby central processor to concurrently perform the same workfunctions, means for comparing data words concurrently generated in saidactive central processor and said standby central processor and forgenerating a trouble signal when said data words do not agree, means insaid central processor system for inhibiting said comparing means, andmeans for causing said active central processor and said standby centralprocessor to operate independently of each other to concurrently performthe same or other system work functions.
 26. In combination, an activecentral processor and a standby central processor, a first dataregister, means in said active central processor for writing a dataconstant in the saId first register, a second data register, means inthe said standby central processor for gating data words from selectedpoints within said standby central processor to said second dataregister, and means for comparing the contents of said first and saidsecond data registers and for generating a match signal when said dataconstant and said gated data word agree.
 27. A central processor systemcomprising a program store containing sequences of program order words,certain of said order words being transfer orders, a data storecontaining system data, a central control comprising means forgenerating code-addresses for obtaining information from said stores andfor writing information into said data store, means for executing saidsequences of program order words, and means responsive to the executionof said transfer orders for recording the code-address of an executedtransfer word and the code-address of the order word to which transferis made.
 28. A system in accordance with claim 27 wherein said centralcontrol further comprises first and second register means, and whereinsaid means responsive to the execution of said transfer orders comprisesmeans for writing said code-address of the executed transfer order intosaid first register means and for writing the code-address of the ordertransferred to in said second register means, and means for momentarilyhalting the obtaining of information from said program store and meansfor transmitting the contents of said first and said second registermeans to said data store.
 29. A central processor system comprising amemory system wherein information is duplicated in independent units ofsaid memory system, a central control, duplicate response transmissionmeans interconnecting said memory system and said central control, meansin said central control for generating code-addresses for obtaininginformation from said memory system, command transmission meansinterconnecting said central control and said memory system, means insaid memory system responsive to said code-addresses for transmitting tosaid duplicate response bus systems duplicate information defined bysaid code-addresses, and means for comparing the data words concurrentlyoccurring on said duplicate response transmission buses and forgenerating a trouble signal whenever said data words disagree.
 30. Acentral processor system comprising an active central processor and astandby central processor each having a plurality of corresponding dataword sources, means in said central processor system for causing saidactive central processor and said standby central processor toconcurrently perform the same sequences of system work functions,matching means for comparing data words gated thereto, means forgenerating a trouble signal when said compared data words do not agree,a match control circuit comprising a point match register and a timeoutregister, means in said central processor system for setting said pointmatch register and said timeout register to selected states, a timeoutcounter, clock means defining a machine cycle and a plurality of phaseswithin said machine cycle, means for incrementing said timeout counteronce every machine cycle, means for comparing the states of said timeoutregister and said timeout counter for generating a match signal when thestates of said counter and said timeout register agree, and meansresponsive to said match signal for selectively gating to said matchingmeans data words obtained from corresponding data word sources of saidprocessors and defined by the states of said point match register.
 31. Acentral processor system in accordance with claim 30 wherein said matchcontrol circuit further comprises a phase match register and saidcentral processor system comprises means for setting said phase matchregister to selected states and said means responsive to said matchsignal is also responsive to the state of said phase match register togate said data words to said matching means during a phase of saidmachine cycle defined by the state of said phase match register.
 32. Acentral processor system in accordance with claim 30 wherein saidcentral processor system further comprises operational checking meansfor detecting faulty responses of said central processor system forgenerating trouble signals upon occurrence of a faulty response,remedial means responsive to said trouble signal for carrying outremedial system work functions and means responsive to said remedialmeans for inhibiting the incrementing of said timeout counter.
 33. Acentral processor system comprising an active central processor and astandby central processor, means in said central processor system forcausing said active central processor and said standby central processorto concurrently perform the same system work functions, means forcomparing data words concurrently generated in said active centralprocessor and said standby central processor and for generating atrouble signal when said data words do not agree, and means in saidcentral processor system responsive to said trouble signal forinhibiting said comparing means and for halting the operation of saidstandby central processor.
 34. A central processor system comprising anactive central processor and a standby central processor, means in saidcentral processor system for causing said active central processor andsaid standby central processor to concurrently perform the same systemwork functions, independent matching means in each of said centralprocessors comprising first and second match registers and a matchcircuit for comparing the contents of said registers and for generatinga trouble signal when said compared contents do not agree, a pluralityof corresponding data word sources in each of said central processors,and independent match control circuits in said active and said standbycentral processors for selectively gating information from saidplurality of data word sources to both of said independent matchingmeans.
 35. A central processor system in accordance with claim 34wherein said match control circuit in said active central processorselectively gates information from data word sources within said activecentral processor to said first match register within said activecentral processor and to said second match register within said standbycentral processor and wherein said match control circuit in said standbycentral processor selectively gates information from said plurality ofdata word sources within said standby central processor to said firstmatch register within said standby central processor and to said secondmatch register within said active central processor.
 36. In combination,a central data processor comprising a central control system havingfirst and second central controls, a semipermanent memory arrangementcomprising a plurality of independent memory units, said centralcontrols and said semipermanent memory units linked by duplicated inputand output bus systems for transmitting commands from said centralcontrols to said semipermanent memory units and for transmittingresponses from said memory units to said central controls, and atemporary memory arrangement comprising a plurality of independenttemporary memory units and duplicated input and output bus systemsinterconnecting said central controls and said temporary memory unitsfor transmitting commands from said central controls to said temporarymemory units and for transmitting responses from said temporary memoryunits to said central controls.
 37. In combination, a memory systemcontaining sequences of program order words and system data, and activeand standby central controls; each of said central controls comprisingmeans for obtaining information from said mEmory system, and means forexecuting said sequences of program order words; means in said activecentral control for generating stop and start signals, transmissionmeans interconnecting said active central control and said standbycentral control for transmitting said stop and start signals, means insaid standby central control responsive to said stop signal for haltingthe execution of said sequences of program order words by said standbycentral control, and means in said standby central control responsive tosaid start signals to initiate execution of said sequences of programorder words by said standby central control.
 38. The combination inaccordance with claim 37 wherein said stop signals comprise fast stopsignals and delayed stop signals and wherein said means in saidstandby-central control responsive to said stop signals comprises a stopsequencer, said sequencer responsive to said delayed stop signals tohalt execution of said program order words by said standby-centralcontrol after said standby-central control has completed work operationsdefined by the order word being executed at the time said delayed stopsignal was received, and said sequencer responsive to said fast stopsignal to halt the execution of said sequences of order words withoutdelay.
 39. The combination system in accordance with claim 38 whereineach of said central controls comprises a plurality of flip-flopregisters and said sequencer in said standby-central control in responseto said fast stop signal generates reset signals for resetting certainof said plurality of flip-flop registers in said standby-centralcontrol.
 40. In combination: a memory arrangement containing programorder words, certain of said order words being control write orderwords, said memory arrangement comprising a plurality of storagelocations dedicated to the storage of program order words, a pluralityof control locations dedicated to the storage of memory controlinformation, and means responsive to control write commands comprisingaddress portions and data portions to gate the data portions of saidcommands to control locations defined by the address portions of saidcommands; and a central control comprising means for obtaining saidprogram order words from said store system, means responsive to saidcontrol write program order words to generate said control writecommands, and means for transmitting said control write commands to saidprogram store system.
 41. The combination in accordance with claim 40wherein said program store system comprises a plurality of programstores and said program store control write command comprises two words,the first of said words comprises a. a multibit code portion definingthe particular program store of said program store system that is toresponse to the command, and b. a mode portion defining the controlwrite mode, said second word comprises a multibit data portion andwherein said transmission means comprises a plurality of individualtransmission paths for parallel transmission of said first and saidsecond words to said particular program store.
 42. The combination inaccordance with claim 41 wherein said means for executing said commandscomprises decoding means and a data reading sequencer, said data readingsequencer responsive to output signals of said decoding means forgenerating said program store control write command signals and formomentarily inhibiting said decoding means.
 43. In combination, acentral control system comprising first and second central controls,means in said central control system defining said first and secondcentral controls as an active central control and a standby centralcontrol, a program store containing sequences of program order words,certain of said program sequences being normal processing sequences andothers of said sequences being maintenance program sequences, a datastore containing system data EACH of said central controls comprisingmeans for obtaining said sequences of order words from said programstore and means for executing said sequences, each of said centralcontrols comprising registers for storing said program order words and aplurality of flip-flop registers, said maintenance program sequencesincluding standby-central control control write sequences, said activecentral control includes means responsive to said standby-centralcontrol control write sequences to generate control write commandsignals, said control write command signals comprising: a. a data storewrite command to place described data in a certain memory location insaid data store, b. a standby-central control alerting command, c. adata store read command to read said data store at said certain memorylocation, response transmission means interconnecting said data storeand said active and said standby-central controls, said standby-centralcontrol comprises decoding means responsive to said standby-centralcontrol alerting command for storing in selected ones of said flip-flopregisters said information read from said data store.
 44. Thecombination in accordance with claim 43 wherein said responsetransmission means comprises data store receiving means in said activeand standby-central controls, terminating resistors, and a plurality ofindependent transmission paths serially connecting said data storereceiving means in said active and said standby-central controls andsaid terminating resistors.
 45. A system for automatically controllingthe times at which operation of a data handling means is initiated,comprising timing means operable to different settings representingelapsed time, time entry storage means operable to a settingrepresenting a time entry, means controlled by the data handling meansduring the carrying out of the program for controlling the time entrymeans to store a time entry representing the time at which the nextprogram is to be initiated, start means in the data handling means forplacing the data handling means in operation to carry out a program, andcontrol means controlled by the timing means and the time entry storagemeans and connected to the start means for operating the start meanswhen a predetermined relation exists between the settings of the timingmeans and the time entry means.
 46. The system set forth in claim 45 inwhich the control means includes a plurality of data comparing gatemeans for comparing the settings of the timing means and the time entrystorage means.
 47. The system set forth in claim 45 in which the datahandling means includes address means for supplying address signals andwhich includes, addressable means connected to the time entry storagemeans and the address means and controlled by the address signals forcontrolling the transfer of a time entry into the time entry storagemeans.
 48. The system set forth in claim 47 including addressable resetmeans supplied with address signals from the data handling means andcontrolled by the receipt of a particular address to reset the timeentry storage means.
 49. A system for controlling the periods ofoperation of a data handling unit of the type capable of carrying out asequence of programmed operations in response to actuation of a startmeans and capable of terminating its operation at the conclusion of theprogram, comprising a timing circuit operable to successive settingsrepresenting elapsed time, a time entry storing circuit adjustable todifferent settings under the control of the data handling unitrepresenting future times, comparing means coupled to the timing circuitand the time entry storing circuit for comparing the settings thereof,means coupled to the start means and controlled by the comparing meansfor operating the start means to place the data handling unit inoperation to carry out its program, means for clearing the time entrystoring means, and means controlled by the data handling unit foradjusting the setting of the cleared time entry storing means to a newsetting in dependence on the next time at which the data handling unitis to be started.
 50. A data processor comprising: means for selectivelyperforming data processing functions, storage means for storing datarepresenting future time, means for entering data in said storage means,timing means for generating output signals representing present time,means for comparing said timing means output signals and said datarepresenting future time to generate a timeout signal when a matchoccurs, means responsive to said timeout signal to effect a change inthe performance of data processing functions by said processor.
 51. Adata processor in accordance with claim 50 wherein said change in theperformance of data processing functions includes the initiation of dataprocessing functions not being performed prior to the occurrence of saidmatch.
 52. In combination: a memory system comprising a plurality ofindependent memory units; a central processor system comprising aplurality of data processors; a transmission bus system forinterconnecting said memory system and said central processor system andcomprising a plurality of independent transmission paths, each of saidindependent transmission paths being selectively connectable to each ofsaid data processors and each of said memory units; register means forstoring information defining a plurality of subsystems, each subsystemcomprising a selected one of said memory units, a selected one of saiddata processors, and a selected one of said independent transmissionpaths; and means for connecting said selected memory unit and saidselected processor to said selected transmission path in accordance withinformation stored in said register means.
 53. A data processing systemcomprising: an active central processor and a standby central processoreach comprising a central control unit and an associated memory unithaving a plurality of addressable locations, each central control unitcomprising means for reading the addressable locations of the associatedmemory unit, means responsive to information read from said locations toperform prescribed data processing functions, and operational checkingmeans for checking the validity of information read from said locationsand for generating an invalidity signal upon the detection of invalidinformation; and means for causing said active and said standby centralprocessors to concurrently perform identical data processing functionscomprising a remedial means responsive to an invalidity signal generatedby either of said operational checking means to cause both of saidcentral control units to again read the location from which the invalidinformation was obtained.
 54. A data processing system comprising: apair of central processors each comprising indicator means andassociated execution means, said indicator means each having two stablestates and said execution means being responsive to one stable state ofthe associated indicator means to perform certain predeterminedoperations and responsive to the other stable state of the associatedindicator means to perform other predetermined operations; and means forconcurrently setting said indicator means to said stable states on amutually exclusive basis, whereby the indicator means of a first centralprocessor is set to one stable state while the indicator means of theother central processor is set to the other stable state.
 55. A dataprocessing system in accordance with claim 54 wherein said systemfurther comprises a plurality of input-output units and transmissionmeans for interconnecting said processors and said input-output units,and wherein each of said processors comprises command signal generatingmeans for generating and transmitting input-output command signals, Saidcommand signal generating means being responsive to the first state ofsaid indicator means to generate and transmit said input-output commandsignals and responsive to the second state of said indicator means toinhibit the transmission of said input-output command signals.